Design of a 12-bit 1 MS/s SAR-ADC for front-end readout of 32-channel CZT detector imaging syst em

作者：Liu, Wei^*; Wei, Tingcun; Li, Bo; Guo, Panjie; Hu, Yongcai

来源：Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment , 2015, 786: 155-163.

DOI：10.1016/j.nima.2015.03.049

• SAR-ADC
• CZT detector
• ASIC
• Front-end readout
• Radiation-hardened design

A 12 bit 1MS/s SAR-ADC for the front-end readout of a 32-channel CZT detector imaging system is presented. In order to improve the performances of the ADC, several techniques are proposed. First, a novel offset cancellation method for comparator is proposed, in which no any capacitor is introduced in the signal pathway, thus it has faster operation speed than traditional one. Second, the architecture of unit capacitor array is adopted in the charge-redistribution DAC to reduce the capacitor mismatch. Third, the radiation-hardened ability is enhanced through circuit and layout design. The prototype chip was fabricated using a TSMC 0.35 urn 2P4M CMOS process. At a 3.3/5 V power supply, the proposed SAR-ADC achieves 67.64 dB SINAD at 1MS/s, consumes 10 mW power and occupies a core area of 1180 x 1080 um(2).

• 出版日期2015-6-21
• 单位西北工业大学