Modular fault tolerant processor architecture on a SoC for space

作者：Tabero Jesus; Regadio Alberto^*; Perez Cesar; Pazos Jesus; Reviriego Pedro; Sanchez Macian Alfonso; Antonio Maestro Juan

来源：Microelectronics Reliability, 2018, 83: 84-90.

DOI：10.1016/j.microrel.2018.02.011

• Single event functional interrupt
• Single event upset
• Error correction
• Fault tolerant systems

Due to configurability feature and increasingly complex architecture, FPGAs have brought advantages to many applications such as avionics and safety critical aerospace, allowing in system reconfiguration after launch. Commercial FPGAs suffer from radiation-induced failures, which are provoked by high-energy particles in space; for this reason, fault tolerant techniques are necessary to harden these devices. This paper presents a design of a fault tolerant multicore processor architecture based on a novel modular voting strategy that fits in FPGAs and System-on-Chip (SoC) devices with an even number of processors. This architecture is implemented within a Commercial off-the-shelf (COTS) SoC that will allow to be used safely in space missions. To harden the fault tolerance of the embedded multicore processor architecture different fault tolerance techniques are combined.

• 出版日期2018-4