A Continuous-Time 0-3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS

作者：Dong Yunzhi^*; Yang William; Schreier Richard; Sheikholeslami Ali; Korrapati Sudhir

来源：IEEE Journal of Solid-State Circuits, 2014, 49(12): 2868-2877.

DOI：10.1109/JSSC.2014.2364829

• Delta-sigma
• MASH
• continuous-time
• CTDS
• ADC
• 0-X MASH
• CT MASH

We present design and measurement details for a 0-3 multi-stage noise-shaping (MASH) ADC that achieves a dynamic range of 88 dB over 53 MHz signal bandwidth. The ADC utilizes a zeroth-order front-end, i.e., a 17-level flash ADC, to perform a coarse quantization and a third-order 7-level continuous-time Delta Sigma back-end to digitize the residue error of the front-end. The ADC achieves the high thermal noise power efficiency of a continuous-time feedforward Delta Sigma modulator and the flat signal transfer function of a flash ADC. The test chip, implemented in a 28 nm CMOS process, clocks at 3.2 GHz. The average noise spectral density with small input signals is - 167 dBFS/Hz and the dynamic range is 88 dB. The test chip ADC consumes a total power of 235 mW from triple power supplies of 0.9/1.8/-1.0 V. The thermal-noise figure-of-merit, defined as FOM = DR + 10log(10) (BW/P) is 171.6 dB.

• 出版日期2014-12