A low impedance receiver for power efficient current mode signalling across on-chip global interconnects

作者：Wary Nijwm^*; Mandal Pradip

来源：AEU-International Journal of Electronics and Communications, 2014, 68(10): 969-975.

DOI：10.1016/j.aeue.2014.04.023

• Current-mode
• Low input impedance
• Self-termination
• Global interconnect

In this work we propose a low impedance receiver for on-chip high speed current-mode signalling over global interconnect. The receiver provides a very low input impedance even with a low quiescent power. The low input impedance helps to get high link bandwidth without any passive terminator. Moreover, the receiver has high transimpedance gain over a large bandwidth. This facilitates in reducing the signalling current by 6.7 times compared to a passive termination. A test chip has been fabricated in 0.18 mu m CMOS process to test the topology with a prototype global interconnect having a length of 10 mm. Power consumption of the transceiver for a data rate of 2.5 Gbps data is 2 mW. This gives an energy efficiency of 0.8 pJ/b.

• 出版日期2014