A Processor and Cache Online Self-Testing Methodology for OS-Managed Platform

作者：Lin Ching Wen^*; Chen Chung Ho

来源：IEEE Transactions on Very Large Scale Integration Systems, 2017, 25(8): 2346-2359.

DOI：10.1109/TVLSI.2017.2698506

• Design for testing (DFT)
• guardband
• online testing
• software-based self-test (SBST)
• transistor aging

Software-based self-test (SBST) is an effective method to detect operational faults of a processor system. We propose an architectural approach to support high fault-coverage online SBST: Processor Shield, which tackles the difficult-to-test issues raised due to the protection of an operating system. The processor shield, including a software framework and design for testing hardware, creates an online self-testing environment without influencing other processes and on-bus devices even if the SBST fails. We present a case study that demonstrates SBST executions under Linux kernel on an ARMv5-compatible processor system. For CPU testing, the stuck-at fault coverage is over 99% while the transition fault coverage is higher than 93%. For cache control logic testing, the stuck-at fault coverage is over 99% while the transition fault coverage is higher than 95%. For RAM module testing, the fault coverage is nearly 100%. Cache SBSTs finish in a context-switch interval of less than 4 ms while CPU SBST finishes in less than 8 ms for 1-GHz clock. The hardware overhead of the processor shield is only 0.494% of the whole processor area. We also present an SBST-dynamic voltage and frequency scaling application that calibrates the dynamic minimal guardbands and helps achieving lower power consumption and mitigating transistor-aging effect.

• 出版日期2017-8