A high-speed four-phase clock generator for low-power on-chip SerDes applications

作者：Zid Mounir^*; Scandurra Alberto; Tourki Rached; Pistritto Carlo

来源：Microelectronics Journal, 2011, 42(9): 1049-1056.

DOI：10.1016/j.mejo.2011.06.012

• Multiphase clocks
• Four-phase clock generator
• High-speed devices
• Parallel architectures
• Low-power architectures
• SerDes

In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for on-chip SerDes applications. The device utilizes a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65 nm process technology using only 125 transistors and it occupies an active area of under 2.34 mu m(2). With a power supply of 1.1 V the complete circuit consumes 89.56 mu W at room temperature.

• 出版日期2011-9