Size-energy tradeoffs for unate circuits computing symmetric Boolean functions

作者：Uchizawa Kei^*; Takimoto Eiji; Nishizeki Takao

来源：Theoretical Computer Science, 2011, 412(8-10): 773-782.

DOI：10.1016/j.tcs.2010.11.022

• Energy complexity
• Parity function
• Size-energy tradeoff
• Symmetric Boolean functions
• Threshold circuits
• Unate circuits

A unate gate is a logical gate computing a unate Boolean function, which is monotone in each variable. Examples of unate gates are AND gates, OR gates, NOT gates, threshold gates, etc. A unate circuit C is a combinatorial logic circuit consisting of unate gates. Let f be a symmetric Boolean function of n variables, such as the Parity function, MOD function, and Majority function. Let m(0) and m(1) be the maximum numbers of consecutive 0's and consecutive 1's in the value vector of f, respectively, and let l = min{m(0), m(1)} and m = max{m(0), m(1)}. Let C be a unate circuit computing f. Let s be the size of the circuit C, that is, C consists of s unate gates. Let e be the energy of C, that is, e is the maximum number of gates outputting "1" over all inputs to C. In this paper, we show that there is a tradeoff between the size s and the energy e of C. More precisely, we show that (n + 1 - l)/m <= s(e). We also present lower bounds on the size s of C represented in terms of n, 1 and m. Our tradeoff immediately implies that log n <= e logs for every unate circuit C computing the Parity function of n variables.

• 出版日期2011-3-4