A Wide Voltage Range Digital I/O Design Using Novel Floating N-Well Circuit

作者：Wang, Chua Chin^*; Hsu, Chia Hao; Liao, Szu Chia; Liu, Yi Cheng

来源：IEEE Transactions on Very Large Scale Integration Systems, 2011, 19(8): 1481-1485.

DOI：10.1109/TVLSI.2010.2049668

• Dynamic gate bias
• floating N-well
• mixed-voltage
• wide-range input/output (I/O) buffer

A fully bidirectional mixed-voltage input/output (I/O) buffer using a novel floating N-well circuit is presented. To provide appropriate gate voltages for output stage transistors, a dynamic gate bias generator without gate-oxide overstress effect is implemented. The proposed I/O also takes advantage of a novel gate-tracking circuit and a PAD voltage detector by means of eliminating the leakage current such that the compatibility among all subcircuits is ensured. Our design is proved on silicon using 0.18 mu m CMOS process that when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, the maximum data rate is found to be 80/80/125/100/80 MHz, respectively, with a given capacitive load of 10 pF.

• 出版日期2011-8
• 单位中山大学