A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC

作者：Samarah Amer^*; Carusone Anthony Chan

来源：IEEE Journal of Solid-State Circuits, 2013, 48(8): 1829-1841.

DOI：10.1109/JSSC.2013.2259031

• Bang bang
• code density test
• coarse-fine time-to-digital converter (TDC)
• digital loop filter
• digital phase-locked loop (DPLL)
• digitally controlled oscillator (DCO)
• nonlinearities
• stochastic TDC
• TDC calibration

A coarse-fine time-to-digital converter (TDC) is presented with a calibrated coarse stage followed by a stochastic fine stage. On power-up, a calibration algorithm based on a code density test is used to minimize nonlinearities in the coarse TDC. By using a balanced mean method, the number of registers required for the calibration algorithm is reduced by 30%. Based upon the coarse TDC output, the appropriate clock signals are multiplexed into the stochastic fine TDC. The TDC is incorporated into a 1.99-2.5-GHz digital phase-locked loop (DPLL) in 0.13-mu m CMOS. The DPLL consumes a total of 15.2 mW of which 4.4 mW are consumed in the TDC. Measurements show an in-band phase noise of - 107 dBc/Hz which is equivalent to 4-ps TDC resolution, approximately an order of magnitude better than an inverter delay in this process technology. The integrated random jitter is 213 fs rms for a 2-GHz output carrier frequency with 700-kHz loop bandwidth. The calibration reduces worst-case spurs by 16 dB.

• 出版日期2013-8