A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register

作者：Ho Yung Hsiang; Yao Chia Yu

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(2): 759-763.

DOI：10.1109/TVLSI.2015.2407577

• All-digital delay-locked loop (ADDLL)
• deskew buffer
• digital-controlled delay line (DCDL)
• successive-approximation register (SAR)
• synchronization

This brief presents a fast-acquisition 11-bit all-digital delay-locked loop (ADDLL) using a novel starting-bit prediction algorithm for the successive-approximation register (SBP-SAR). It can effectively eliminate the harmonic lock and the false lock. The achievable acquisition time is within 17.5-23.5 or 17.5-32.5 clock cycles when the ADDLL works at the low or high clock rate, respectively. The digital-controlled delay line and the SBP-SAR of the ADDLL chip are synthesized using Taiwan Semiconductor Manufacturing Company's (TSMC's) 0.18-mu m CMOS cell library. The proposed ADDLL can operate at a clock frequency from 60 MHz to 1.1 GHz.

• 出版日期2016-2