摘要

The unique features of single-electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor hybrid circuit have attracted much attention in recent years. A novel octal-to-binary encoder using single-electron and MOS transistors is proposed. It consists of three PMOS transistors, three NMOS transistors, and three SETs. The operation of the proposed circuit is successfully confirmed through HSPICE simulation based on the compact macro model of SET. Simulation results show that the hybrid SET/MOS encoder has the advantages of low power consumption and large load capability. The power dissipation is only 24.9 nW. Compared to the pure SET octal-to-binary encoder, whose output voltage swing is merely 0.00 2V, the proposed hybrid SET/MOS circuit has an output voltage swing as high as 0.67 V, which is more suitable for the future digital very large scale integrated circuit application. The effects of noise fluctuations, operating temperature, and integration issue are discussed to evaluate the performance of the proposed hybrid SET/MOS encoder circuit.

全文