科研之友
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摘要
A simple circuit for duty-cycle correction is proposed in this paper. The configuration is flexible consisting of only three CMOS inverters in a feedback loop. It does not require any reference signal and, therefore, it can be used as a standalone circuit, while it can be applied on a single-ended clock path without breaking the clock line. Simulation results in a 65 nm CMOS technology and 1 V supply voltage give a duty-cycle error less than 1% for a duty-cycle input clock variation between 30 and 70% with a frequency range from 2.4 to 2.9 GHz.
- 出版日期2017-3
