An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 8 x 8 Point EEG/MEG Acquisition System

作者：Eo Ji Hun^*; Jeong Yeon Ho; Jang Young Chan

来源：IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2013, E96A(2): 453-458.

DOI：10.1587/transfun.E96.A.453

• successive approximation
• analog-to-digital converter
• time-domain comparator
• daisy channel

An 8-bit 100-kS/s successive approximation (SA) analog-to-digital converter (ADC) is proposed for measuring EEG and MEG signals in an 8 x 8 point. The architectures of a SA ADC with a single-ended analog input and a split-capacitor-based digital-to-analog converter (SC-DAC) are used to reduce the power consumption and chip area of the entire ADC. The proposed SA ADC uses a time-domain comparator that has an input offset self-calibration circuit. It also includes a serial output interface to support a daisy channel that reduces the number of channels for the multi-point sensor interface. It is designed by using a 0.35-mu m 1-poly 6-metal CMOS process with a 3.3 V supply to implement together with a conventional analog circuit such as a low-noise-amplifier. The measured DNL and INL of the SA ADC are +0.63/-0.46 and +0.46/-0.51 LSB, respectively. The SNDR is 48.39 dB for a 1.11 kHz analog input signal at a sampling rate of 100 kS/s. The power consumption and core area are 38.71 mu W and 0.059 mm(2), respectively.

• 出版日期2013-2