A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement

作者：Chen, Liang Bi^*; Yeh, Chi Tsai; Chen, Hung Yu; Huang, Ing Jer

来源：IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2009, E92A(12): 3193-3202.

DOI：10.1587/transfun.E92.A.3193

• design space exploration
• system-on-a-chip (SoC)
• SystemC
• UML
• 3D graphics

3D graphics application is widely used in consumer electronics which is an inevitable tendency in the future. In general, the higher abstraction level is used to model a complex system like 3D graphics SOC. However, the concerned issue is that how to use efficient methods to traverse design space hierarchically, reduce simulation time, and refine the performance fast. This paper demonstrates a system-level design space exploration model for a tile-based 3D graphics SoC refinement. This model uses UML tools which can assist designers to traverse the whole system and reduces simulation time dramatically by adopting SystemC. As a result, the system performance is improved 198% at geometry function and 69% at rendering function, respectively.

• 出版日期2009-12
• 单位中山大学