科研之友
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摘要
A novel procedure is introduced for designing Doherty amplifiers using the model-based nonlinear-embedding technique. First, the Doherty intrinsic load-matching network is designed at the transistor current-source reference plane with the main and auxiliary devices interconnected. Identical devices with different biasing are used for realizing an asymmetric Doherty implementation with 9-dB back-off. The required multiharmonic impedances at the package planes are then obtained using the embedding device model for both devices, and the complex load impedance at the fundamental is projected back to resistive loads using an offset line. An even-number multisection impedance transformer and a reduced drain voltage of the main amplifier are used to design the asymmetric Doherty load network while providing the necessary loads to the main and auxiliary devices. The optimization of the drain efficiency and gain curves of the asymmetric Doherty operation for the proposed design is further investigated by adjusting the auxiliary gate-bias. An efficiency above 50% over an 11-dB power range is experimentally observed with 41.8-dBm peak output power using continuous wave (CW) at 2 GHz. Using a dual-input implementation of the designed Doherty power amplifier (PA), a systematic dual-input CW characterization of the Doherty operation is performed to establish the relative auxiliary-to-main phase offsets and power offsets yielding a maximum efficiency under constant gain. From this dual-input characterization, it is found that the optimal gate bias for single-input Doherty operation is the one for which the constant-gain maximum efficiency is achieved for a quasi-constant auxiliary-to-main input power ratio corresponding to the one implemented in the input divider in the single-input Doherty PA.
- 出版日期2014-12
