A Blind Baud-Rate ADC-Based CDR

作者：Ting Clifford^*; Liang Joshua; Sheikholeslami Ali; Kibune Masaya; Tamura Hirotaka

来源：IEEE Journal of Solid-State Circuits, 2013, 48(12): 3285-3295.

DOI：10.1109/JSSC.2013.2279023

• ADC-based clock and data recovery (CDR)
• all-digital CDR
• baud-rate CDR
• blind-sampling CDR
• Mueller-Muller PD (MMPD)

This paper proposes a 10-Gb/s blind baud-rate ADC-based CDR. The blind baud-rate operation is made possible by using a 2UI integrate-and-dump filter, which creates intentional ISI in adjacent bit periods. The blind samples are interpolated to recover center-of-the-eye samples for a speculative Mueller-Muller PD and a 2-tap DFE operation. A test chip, fabricated in 65-nm CMOS, implements a 10-Gb/s CDR with a measured high-frequency jitter tolerance of 0.19UI(PP) and +/- 300 ppm of frequency offset.

• 出版日期2013-12