A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die V-th variation

作者：Goudarzi Maziar^*; Ishihara Tohru; Yasuura Hiroto

来源：Microelectronics Journal, 2008, 39(12): 1797-1808.

DOI：10.1016/j.mejo.2008.02.002

• Cache memories
• Leakage currents
• Yield
• Process variation
• Software
• SRAM chips

Exceptionally leaky transistors are increasingly more frequent in nanometer-scale technologies due to lower threshold voltage and its increased variation. SRAM cells containing such transistors suffer from accelerated aging due to electromigration intensified by higher currents continuously flowing through thin metals such as vias and contacts. Such cells do not violate target delay since leaky transistors are faster than ideal ones, and hence they are not faulty to be worth replacing with redundant rows and columns, which may also themselves contain exceptionally leaky transistors. Moreover, their number is growing so fast that makes redundancy ineffective. We show that in SRAM cells leakage current depends on the Value stored in the cell and propose a software-based runtime technique that suppresses such abnormal leakages in the standby mode by storing safe values in the corresponding cache lines. Consequently, the lifetime of such caches is restored when used in long-standby applications. Moreover, energy dissipation in the standby mode is reduced by this technique if the standby duration is more than a few seconds. Analysis proves the performance penalty is, in the worst case, linearly dependent to the number of so-cured cache lines.

• 出版日期2008-12