A high performance low power 12-bit 40 MS/s pipelined ADC

作者：Jia Hua Yu^*; Chen Gui Can; Zhang Hong

来源：IEICE Electronics Express, 2008, 5(11): 400-404.

DOI：10.1587/elex.5.400

• pipelined analog-to-digital converter
• residue amplifier
• common-mode feedback

A 1.8 V 12-bit 40 MS/s pipelined ADC fabricated in a 0.18 mu m CMOS process is presented. The traditional closed-loop high performance residue amplifier in first stage is replaced by a simple open-loop amplifier to reduce power dissipation and increase circuit speed in the paper. To improve the stability and response speed of the amplifier, a novel circuit topology of open-loop amplifier is presented in this study. Also, a proposed (1 + 1)-bit/stage structure for pipelined ADC is used in the paper to convert residue voltage that exceeds the convert range. The occupied silicon area is 3.2 x 3.7 mm(2) and the power consumption equals 210 mW.

• 出版日期2008-6-10
• 单位西安交通大学