Design of SRAM Cell Based Memory Array in Nano-Scaled Technology

作者：Akashe Shyam^*; Sharma Sanjay

来源：Journal of Computational and Theoretical Nanoscience, 2013, 10(6): 1453-1459.

DOI：10.1166/jctn.2013.2871

• SNM
• Power
• Leakage Current
• Access Time

This Paper aims to reduce the read time as well as to increase the SNM and stability of the SRAM cell during read operation. A different 7T cell with single bit line is proposed to increase the SNM and stability within the memory core. A 4 x 4 array is constructed using single ended 7T cell to show the feasibility of the proposed SRAM cell. A 16 Bit SRAM operating at 1 v supply voltage is demonstrated in 45 nnn CMOS process. Its total power consumption is reduced by more than 90% of the conventional design. This 7T cell has lower leakage current due to single bit line and transmission gate at feedback. As a result it is suitable for low power consumption application especially battery operated gadgets.

• 出版日期2013-6