DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems

作者：Cui, Jinhua^*; Zhang, Youtao; Wu, Weiguo; Yang, Jun; Wang, Yinfeng; Huang, Jianhang

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(8): 1546-1559.

DOI：10.1109/TCAD.2017.2766156

• Flash memories
• low-density parity-check code (LDPC)
• out-of-order scheduler
• process variation (PV)
• raw bit error rate (RBER)
• retention age (RA)

NAND flash has been widely adopted in storage systems due to its better read and write performance and lower power consumption over traditional mechanical hard drives. To meet the increasing performance demand of modern applications, recent studies speed up flash accesses by exploiting access latency variations at the device level. Unfortunately, existing flash access schedulers arc still oblivious to such variations, leading to suboptimal I/O performance improvements. In this paper, we propose DLV, a novel Hash access scheduler for exploring scheduling opportunities due to device level access latency variations. DLV improves flash access speeds based on process variations and data retention time difference across flash blocks. More importantly, DLV integrates access speed optimization with access scheduling such that the average access response time can be effectively reduced on flash memory storage systems. Our experimental results show that DIN achieves an average of 41.5% performance improvement over the state-of-the-art.

• 出版日期2018-8
• 单位西安交通大学; 深圳信息职业技术学院