A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment

作者：Gonzalez Diaz Victor R^*; Munoz Pacheco Jesus M; Espinosa Flores Verdad Guillermo; Sanchez Gaspariano Luis A

来源：Radioengineering, 2016, 25(1): 89-97.

DOI：10.13164/re.2016.0089

• Frequency synthesizers
• fractional
• modeling
• sigma-delta
• phase noise
• Verilog-A

This paper presents a new strategy to simulate fractional frequency synthesizer behavioral models with better performance and reduced simulation time. The models are described in Verilog-A with accurate phase noise predictions and they are based on a time jitter to power spectral density transformation of the principal noise sources in a synthesizer. The results of a fractional frequency synthesizer simulation is compared with state of the art Verilog-A descriptions showing a reduction of nearly 20 times. In addition, experimental results of a fractional frequency synthesizer are compared to the simulation results to validate the proposed model.

• 出版日期2016-4