科研之友
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摘要
A 128-channel neural signal processor for implantable neural recording microsystems is presented. The processor compresses the neural information of 128 simultaneous recording channels using discrete cosine transform, achieving a compression factor of 69 at the expense of a 5.6% root mean square error. The proposed processor is implemented on register transfer level and synthesized in a 65-nm complementary metal-oxide semiconductor process. The post-layout simulated power consumption at 1.2V is 33.06W (258nW per channel) at an area cost of 0.46mm(2).
- 出版日期2015-4
