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摘要
In this paper, a most significant bits (MSBs) prediction strategy for the design of successive approximation register (SAR) analog-to-digital converter (ADC) in battery pack voltage detection is proposed to reduce conversion time without losing accuracy. The strategy takes advantage of the battery pack voltages characteristics where there is a strong correlation among neighboring cell voltage values. By generating the MSBs with the quantization results of the battery pack in the previous loop, the ADC just needs to convert the remaining least significant bits (LSBs). This paper analyzes the relationship between saved time and five parameters: reading frequency W, cell number of battery pack (N), cell number (CN) for MSB-prediction, standard deviation (sigma), change rate of digital number (K), which can give a feasible prediction on saved working time in any conditions. With this strategy, in a f= 50 kHz, N = 10, CN = 8, sigma = 10 system, up to 27.83% A/D conversion time can be saved in charging state, and 27.89% A/D conversion time can be saved in discharging state.
