Fast and accurate FPGA-based framework for processor architecture vulnerability analysis

作者：Mahdiani Hoda; Safari Saeed; Salehi Mostafa E^*

来源：Integration, the VLSI Journal, 2016, 53: 14-26.

DOI：10.1016/j.vlsi.2015.11.005

• Architecture Vulnerability analysis
• Soft error
• Embedded processors
• Fault modeling and emulation
• Field-programmable gate array

This paper presents a fast, accurate, and flexible FPGA-based fault emulation platform, namely FARAVAM that can be exploited for AVF analysis in modern microprocessors. The proposed approach provides fault injection capabilities supporting automatic modification of post-synthesis net-lists and introduces a highly controllable and observable transient fault analysis environment. The presented vulnerability analysis platform using both exhaustive and random fault emulation approaches, provides useful information for identifying areas threatening reliability to make processors more fault tolerant. We applied our platform for extracting the best trade-offs between precision and speed up in vulnerability analysis of MIPS processor. The experimental results indicate that in addition to having high precision we obtain about seven orders of magnitude speed up in comparison with simulation based vulnerability analysis techniques.

• 出版日期2016-3