A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

作者：Won Hyosup^*; Yoon Taehun; Han Jinho; Lee Joon Yeong; Yoon Jong Hyeok; Kim Taeho; Lee Jeong Sup; Lee Sangeun; Han Kwangseok; Lee Jinhee; Park Jinho; Bae Hyeon Min

来源：IEEE Journal of Solid-State Circuits, 2015, 50(2): 399-413.

DOI：10.1109/JSSC.2014.2369494

• Clock and data recovery (CDR)
• delay-and phase-locked loop (D/ PLL)
• input sensitivity
• jitter tolerance (JTOL)
• jitter transfer (JTRAN)
• low power
• phase rotator
• serial link
• transceiver
• 100 Gigabit Ethernet

This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay-and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line (T-line) and quadrate RX and TX schemes without CML logic gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from 478 mV(ppd) to 1.06 V-ppd. RX equalizers employing a continuous-time linear equalizer and a one-tap decision feedback equalizer compensate for the channel loss up to 25 dB at the Nyquist rate. The measured RX input sensitivity for a BER of 10(-12) is 42 mV(ppd). The proposed IC consumes only 0.87 W at 28.0 Gb/s with a BER less than 10(-15) on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.

• 出版日期2015-2