An 8-bit 12.5-GSample/s SiGe ADC

作者：Ghetmiri Shohreh^*; Salama C A T

来源：Analog Integrated Circuits and Signal Processing, 2010, 63(3): 381-395.

DOI：10.1007/s10470-009-9422-7

• Analog to digital converter
• Folding-interpolating
• High speed
• SiGe

This paper describes the design of a high-speed 8-bit Analog to digital converter (ADC) used in direct IF sampling receivers for satellite communication systems in a 0.25 mu m, 190 GHz SiGe BiCMOS process. A high resolution front-end track-and-hold amplifier (THA), a low impedance reference and interpolation resistive ladder and high resolution comparators enable the ADC to achieve good performance for input frequencies of up to one-quarter of the sampling rate. The final post layout simulated system features an ENOB of 7.2-bits at an input frequency of 3.125 GHz and a sampling rate of 12.5 GS/s with a FOM of 12.9 pJ per conversion. Both DNL and INL are within 0.5 and 1 LSB, respectively. The converter occupies 10 mm(2) and dissipates 14 W from a 3.3 V supply. The THA and the comparator, as the most critical building blocks affecting the overall performance of the ADC, were implemented experimentally and fully characterized in order to verify their performance and to ascertain the possibility of implementing the complete ADC. The THA occupies an area of 0.5 mm(2). It features a SNDR of 47 dB or 7.5-bits ENOB for a 3 GHz bandwidth, a hold time of 21 ps with a droop rate of 11 mV/80 ps and a power dissipation of 230 mW from a 3.3 V supply. The comparator occupies an area of 0.38 mm(2) and exhibits an input sensitivity of +/- 2 mV, an input offset voltage of 1.5 mV, latch and recovery times of 19 and 21 ps, respectively, and a power dissipation of 150 mW from a 3.3 V supply. The experimental results are in good agreement with simulation and expected specifications and indicate that both circuits are suitable for the implementation of the ADC and help to validate that the 8-bit 12.5 GS/s ADC is feasible for implementation in a 0.25 mu m SiGe process.

• 出版日期2010-6