A highly linear CMOS buffer based on third harmonic cancellation

作者：Mousazadeh Morteza^*; Hadidi Khayrollah; Khoei Abdollah

来源：Analog Integrated Circuits and Signal Processing, 2016, 86(2): 207-213.

DOI：10.1007/s10470-015-0653-5

• Buffer
• Linearization
• Third harmonic neutralization
• Source follower

An open loop high speed CMOS differential source follower buffer with improved linearity and negligible extra power consumption in comparison to conventional one is presented. The conventional linear buffers which are commonly implemented in closed loop structure limits the maximum achievable frequency. On the other hand, linearity of differential open loop buffers (source followers) is restricted due to the third harmonic distortion. The proposed differential source follower buffer improves linearity by directly neutralizing third harmonic distortion. Also, a strict analysis on the third harmonic distortion is organized which confirms considerable linearity improvement. The new buffer achieves 86 dB linearity for a 100 MHz 1.6 Vp-p output amplitude, with 2 pF load capacitor at each side in other wise 77 dB linearity of conventional buffer, 95 dB linearity for a 100 MHz 1.0 Vp-p output amplitude in other wise 85 dB linearity of conventional one and 84 dB linearity at dual-tone input frequency in other wise 74.7 dB linearity of conventional one. The power consumption of the proposed buffer is 48 mw while the conventional buffer consumes 42 mw which means about 14 % increases in power consumption leads to 10 dB linearity improvement. The buffer is implemented by using 0.35 mu m dual-poly quadruple metal CMOS technology.

• 出版日期2016-2