摘要

A 400 Mb/s similar to 2.5 Gb/s referenceless clock and data recovery (CDR) IC is presented. This paper shows that the half-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability in itself. By using this intrinsic frequency detection capability of the half-rate linear PD, a CDR can be implemented in the single loop architecture without both an external reference clock and a separate frequency detector. For verification, a prototype CDR IC was fabricated in a 0.13 mu m CMOS process. With 2.5 Gb/s, 2(31) - 1 pseudorandom binary sequence (PRBS), the measurement results show that the frequency acquisition time is 17 mu s, the bit error rate (BER) is better than 10(-12), the jitter of the recovered clock is 8.6 ps(rms) and the out-of-band jitter tolerance is 0.32 UIpp.

  • 出版日期2016-10