摘要

This paper investigates a clock frequency generator for ultra-low-voltage sub-picosecond-jitter clock generation in future 0.5-V LSI and power aware LSI. To address the potential possible solution for ultra-low-voltage applications, a 0.5 V clock frequency generator is proposed and implemented. Significant performances, in terms of sub 1-ps jitter, 50 MHz-to-6.4 GHz frequency tuning range with 2 bands and sub 1-mW P-DC, demonstrated the viable replacement of ring oscillators in low-voltage and low-jitter clock generator.

  • 出版日期2012-7

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