A12b, 40-MS/s, 4.1mW fully differential CBSC pipelined ADC in 0.18 mu m CMOS

作者：Zamani Majid^*; Jafarabadi Ashtiani Shahin; Dousti Masoud; Naser Moghadasi Mohammad

来源：IEICE Electronics Express, 2010, 7(23): 1714-1720.

DOI：10.1587/elex.7.1714

• CBSC
• fully differential architecture
• pipeline ADC
• low-power design
• preset levels designing
• offset regulating

In this paper a fully differential comparator-based switched-capacitor (CBSC) pipelined ADC is presented. For better performance and accuracy, we modified the differential architecture and introduced some practical issues on preset levels designing. For comparison, we used a simple comparator which can compensate offset easily. Finally we designed a 12b 40 MS/s Fully Differential CBSC Pipelined ADC with proposed architecture in a 0.18-mu m standard CMOS process. It achieves 75.2-dB spurious-free-dynamic range (SFDR) and 69.78-dB SNDR. In addition it consumes 4.1mW from a 1.8-V power supply at 40 MS/s, which obtains a figure of merit of 460 fJ/step.

• 出版日期2010-12-10