科研之友
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摘要
A common-gate (CG) transistor in a cascode power amplifier has a large input capacitance variation in the saturation region with respect to the source voltage. This causes large nonlinearity in a CMOS PA that utilizes a cascode configuration. Here, we propose a method to reduce the capacitance variation by introducing a parallel auxiliary transistor that works in both the saturation and depletion regions by applying a bias voltage that is slightly different from the main one. This provides the proposed CMOS PA a gain of 27.8 dB and an output power of 16.7 dBm with a PAE of 14.7% for an 802.11n modulated signal with an EVM of -25 dB.
- 出版日期2017-1
