An MWPC readout chip for high rate environment

作者：Kano H^*; Fukunaga C; Ikeno M; Sasaki O; Sato K; Matsuura S

来源：IEEE Transactions on Nuclear Science, 2001, 48(3): 509-513.

DOI：10.1109/23.940108

• application-specified integration circuit (ASIC)
• pipeline
• synchronization
• trigger
• VME bus

An application-specified integration circuit (ASIC) has been fabricated in order to readout data from a multiwire proportional chamber (MWPC) that is installed in a high-rate environment. 16 channels and an ancillary control circuit are packed in a chip, and a channel consists of an LVDS receiver and 100-stage shift register array for delay. Hit data from the chamber is once inputted in the shift register array, and is outputted when the trigger signal is set. If a channel contains a signal during a gate followed by the trigger, the channel is regarded as containing a hit. The primary purpose for constructing the chip is for test beam and cosmic ray test of ATLAS thin gap chambers (TGC), which are used for the muon-trigger signal generation. The architecture of the ASIC is simple and independent from the specific readout scheme of ATLAS TGC. It will be found that the ASIC is adopted easily for any readout scheme of MWPC like detector.

• 出版日期2001-6