A 0.6 v 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS

作者：Lü Wei; Luo Duona; Mei Fengcheng; Yang Jiaqi; Yao Libin; He Lin^*; Lin Fujiang

来源：Chinese Journal of Semiconductors, 2014, 35(5): 055006.

DOI：10.1088/1674-4926/35/5/055006

• Common mode
• Dynamic comparators
• Low-voltage designs
• Nyquist frequency
• SAR ADC
• Simulations and measurements
• Successive approximation register
• Wireless sensor network applications

This paper presents a 0.6 V 10 bit successive approximation register (SAR) ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 × 300 μm2.

• 出版日期2014
• 单位中国科学技术大学