Design of reconfigurable architectures for multi-standards video decoder

作者：Tan Sisi; Qiao Fei^*; Yang Hua Z; Wang Hui

来源：Recent Patents on Electrical Engineering, 2011, 4(1): 63-70.

• Dynamic re-configuration
• Multi-standard
• Re-configurable
• Reconfigurable hardware architecture
• Video decoders

Digital video decoding is a typical data-intensive video processing application. Currently, high throughput and real time processing are the fundamental demands of performance for video processing systems. With the development of various video standards, multi-standard applications have become another key feature. Thus, the high performance, low area cost and low power consumption make up the most important design targets when realizing video processing chips. Reconfigurable hardware architectures have been reviewed in this paper, which could meet the above requirements for multi-standard video decoders. Traditional reconfiguration methods usually decrease area cost by reconfiguring the interconnections among function units. A relatively new approach is dynamic reconfiguration, which could reconfigure hardware resources at runtime. Recently, a new method called Reconfigurable Video Coding (RVC) has come up, which is a library-based method to design a reconfigurable system for multi-standard video decoders. An overview of the methodologies for reconfigurable video processing system is shown in the paper, as well as case studies, which demonstrate the effectiveness of the design flow. The article presents some promising patents on design of reconfigurable architectures for multi-standards video decoder.

• 出版日期2011
• 单位清华大学