摘要

The thermal stress of typical integrated circuit (IC) integration with the interposer of through silicon via (TSV) was investigated in this study. To overcome the huge computational costs due to meshing the large amount of TSVs' microstructures, a simplified method, i.e. the complement sector model, was proposed and verified by the symmetric 1/8th full model. Using the sector model, the parametric studies were carried out to reveal the critical locations of TSV and the crucial parameters. Furthermore, statistical methods were invoked to clarify the impact of the major parameters, such as the modulus and coefficient of thermal expansion of underfill materials, the pitch and diameter of TSV, etc. Upon the analysis results, the design of minimized stress in TSV for the IC integration with TSV interposer was achieved.