A Linearity-Improved 8-bit 320-MS/s SAR ADC With Metastability Immunity Technique

作者：Xu, Daiguo; Qiu, Lei^*; Zhang, Zhengping; Liu, Tao; Liu, Lu; Chen, Kairang; Xu, Shiliu

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 26(8): 1545-1553.

DOI：10.1109/TVLSI.2018.2822678

• Analog-to-digital converter (ADC)
• asynchronous successive approximation register (SAR)
• linearity improved
• metastability immunity comparator

This paper presents an 8-bit 320-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with the linearity-improved technique. A linearity-improved sampling switch with parasitic capacitance compensation, which makes the parasitic capacitance of sampling switch to be almost constant with varied input signal, is proposed. It also improves the matching of the differential sampling switches. Moreover, a metastability immunity technique is provided to suppress the uncertain decision behavior of dynamic comparator at high conversion rate. In addition, a bypass SAR logic that parallels comparator and SAR logic operations is exhibited to reduce the delay of SAR feedback loop. To demonstrate the proposed techniques, a design example of SAR ADC is fabricated in a 55-nm CMOS technology, consuming 1.2 mW at a 1-V power supply. It achieves a signal-to-noise-and-distortion ratio > 43.5 dB and spurious free dynamic range > 54 dB at 320 MS/s. The ADC core occupies an active area of only 0.02 mm(2), and the corresponding figure of merit is 30 fJ/conversion step with Nyquist rate.

• 出版日期2018-8
• 单位南阳理工学院; 电子科技大学