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摘要
A wideband package-level driver amplifier in 65 nm CMOS technology is presented in this paper. The inductor-less design is adopted for the inter-stage connection to achieve wide working bandwidth. Bonding wires for the package are modelled and used as the input/output matching networks to minimize the chip size. High-reliability design is adopted and ESD protection circuit, which is able to work under large output voltage swing, are integrated. The proposed amplifier works from 0.72 to 3.65 GHz with 134% fractional bandwidth. The amplifier has 27 dB power gain. The size of the chip is 0.63 x 0.68 mm(2).
- 出版日期2018-6-10
- 单位电子科技大学
