A 30-GHz Power-Efficient PLL Frequency Synthesizer for 60-GHz Applications

作者：Mahalingam, Nagarajan^*; Wang, Yisheng; Thangarasu, Bharatha Kumar; Ma, Kaixue; Yeo, Kiat Seng

来源：IEEE Transactions on Microwave Theory and Techniques, 2017, 65(11): 4165-4175.

DOI：10.1109/TMTT.2017.2699671

• Coupled LC tanks (CLCTs)
• fractional-N
• frequency synthesizer
• low phase noise
• low power
• multimode
• phase-locked loop (PLL)
• silicon-germanium (SiGe)
• 60 GHz
• 30 GHz
• voltage-controlled oscillator (VCO)

This paper presents the design and verification of a proposed 30-GHz power-efficient phase-locked loop (PLL) frequency synthesizer for 60-GHz applications. Fabricated by a commercial 0.18-mu m SiGe BiCMOS process, the synthesizer employs coupled LC tank voltage-controlled oscillator, high power-added efficiency amplifier, reconfigurable divider realizing fractional division ratios for choice of multiple reference frequencies and low operation power, a programmable charge pump, an internal loop filter, and an integrated slave serial peripheral interface. The PLL synthesizer (PLLS) provides output frequency from 29.5 to 33.4 GHz with phase noise of -97 dBc/Hz at 1-MHz offset. The integrated phase noise over the frequency of 10 kHz-10 MHz is 2.05 degrees rms at a frequency of 30.24 GHz. Operating with a single 1.8-V supply voltage, the PLLS consumes a low power of 63 mW and occupies an area of 2.8 mm x 1.86 mm.

• 出版日期2017-11
• 单位电子科技大学