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摘要
A four-lane 12-Gb/s per lane high-definition multimedia interface (HDMI) 2.1 transmitter is developed in 28-nm bulk CMOS process. To relieve the burden of the generation and distribution of clock, quarter-rate architecture is employed where the duty-cycle and phase spacing errors of multi-phase clock are automatically corrected by analog-digital converter based digital logic. The output driver terminated with 3.3-V supply is implemented only with 1.8- and 1.0-V transistors which are protected from over-voltage stress by double-cascoding with adaptive bias generation. The 4-lane HDMI 2.1 transmitter consumes 12.0-mW/lane at 12-Gb/s and occupies 0.12-mm(2) active area.
- 出版日期2018-8
