A 0.7 V input output-capacitor-free digitally controlled low-dropout regulator with high current efficiency in 0.35 mu m CMOS technology

作者：Lo Yu Lung^*; Chen Wei Jen

来源：Microelectronics Journal, 2012, 43(11): 756-765.

DOI：10.1016/j.mejo.2012.07.008

• Digital control
• Low-dropout regulator
• Output-capacitor-free
• Ultralow voltage

This paper presents a discussion on an ultralow supply voltage low-dropout regulator (LDO) using a digitally controlled technique. Based on a 0.351 mu m standard CMOS process with V-TN approximate to 0.5 V and vertical bar V-TP vertical bar approximate to 0.7 V. measurement results showed that the proposed digitally controlled LDO can operate from 0.7 V to 0.9 V with a dropout voltage of 200 mV. At a supply voltage of 0.9 V. the proposed LDO is capable of providing a regulated output of 0.7 V and delivering a maximal load current of 50 mA at 99.9% current efficiency. With the proposed LDO operated at 1 MHz clock, the measured quiescent current is only 4.7 mu A. No external output capacitor is required to stabilize the control loop. For a supply voltage of 0.9 V, the proposed digital LDO features a tunable transient time with a maximal operating frequency up to approximately 14 MHz. The proposed LDO can also operate at supply voltages of 0.7 V in a 0.35 mu m standard CMOS process. For an input voltage of 0.7 V and an output voltage of 0.5 V, the proposed LDO can deliver a maximal load current of 5 mA, which meets the specification of recently published 0.5 V applications. With these advantages, the proposed digitally controlled LDO is suitable for low-voltage and low-power applications.

• 出版日期2012-11