A 4 x 10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS

作者：Lee Joon Yeong^*; Yang Jaehyeok; Yoon Jong Hyeok; Kwon Soon Won; Won Hyosup; Han Jinho; Bae Hyeon Min

来源：IEEE Transactions on Very Large Scale Integration Systems, 2016, 24(6): 2310-2320.

DOI：10.1109/TVLSI.2015.2502957

• Clock and data recovery (CDR)
• frequency-locked loop (FLL)
• masterless
• parallel transceiver
• phase-locked loop (PLL)
• referenceless
• stochastic reference clock generator (SRCG)

A four-parallel 10-Gb/s referenceless-and-masterless phase rotator-based transceiver is presented. Entire lanes operate independently just like the conventional voltage-controlled-oscillator-based parallel referenceless designs while saving power and area. The measured recovered-clock jitter in each lane is 1.24 ps(rms) and the transceiver surpasses the OC-192 jitter-tolerance specification. The power efficiency of the proposed parallel transceiver fabricated in a 90-nm CMOS process is 6.325 mW/(Gb/s).

• 出版日期2016-6