A 4 GHz 60 dB Variable Gain Amplifier With Tunable DC Offset Cancellation in 65 nm CMOS

作者：Kumar Thangarasu Bharatha^*; Ma Kaixue; Yeo Kiat Seng

来源：IEEE Microwave and Wireless Components Letters, 2015, 25(1): 37-39.

DOI：10.1109/LMWC.2014.2361676

• CMOS VGA
• DC offset cancellation
• low power design
• tunable DCOC
• variable gain amplifier (VGA)

This letter presents a compact CMOS based variable gain amplifier with 60 dB gain control range and a feedback reconfigurable dc offset cancellation. The design is a four-stage fully differential cascaded amplifier implemented using a 65 nm CMOS process. The amplifier achieves a current controllable gain range from -39.4 dB to +20.2 dB, a voltage tunable lower cutoff frequency from dc to 200 kHz, a consistent 3 dB bandwidth better than 4 GHz, a maximum dc power consumption of 26 mW, a measured in-band group delay variation of 20 ps, and a noise figure from 10 to 27 dB. The proposed VGA design occupies a compact die area of only 75 mu m 80 mu m (excluding pads for measurement).

• 出版日期2015-1
• 单位南阳理工学院