A 1.2-V 37-38.5-GHz eight-phase clock generator in 0.13-mu m CMOS technology

作者：Cho Lan Chou^*; Lee Chihun; Liu Shen Iuan

来源：IEEE Journal of Solid-State Circuits, 2007, 42(6): 1261-1270.

DOI：10.1109/JSSC.2007.897169

• clock generator
• phase-locked loop (PLL)

A 37-38.5-GHz clock generator is presented in this paper. An eight-phase LC voltage-controlled oscillator (VCO) is presented to generate the multiphase outputs. The high-pass characteristic CL ladder topology sustains the high-frequency signals. The split-load divider is presented to extend the input frequency range. The proposed PD improves the static phase error and enhances the gain. To verify the function of each block and modify the operation frequency, two additional testing components-an eight-phase VCO and a split-load frequency divider-are fabricated using 0.13-mu m CMOS technology. The measured quadrature-phase outputs of VCO and input sensitivity of the divider are presented. This clock generator has been fabricated with 0.13-mu m CMOS technology-The measured rms clock jitter is 0.24 ps at 38 GHz while consuming 51.6 mW without buffers from a 1.2-V supply. The measured phase noise is -97.55 dBe/Hz at 1-MHz offset frequency.

• 出版日期2007-6
• 单位中国科学院电工研究所