A 5.8 GHz Integrated CMOS Dedicated Short Range Communication Transceiver for the Korea/Japan Electronic Toll Collection System

作者：Kwon Kuduck^*; Choi Jaeyoung; Choi Jeongki; Hwang Yongseok; Lee Kwyro; Ko Jinho

来源：IEEE Transactions on Microwave Theory and Techniques, 2010, 58(11): 2751-2763.

DOI：10.1109/TMTT.2010.2077891

• Dedicated short range communication (DSRC)
• electronic toll collection system (ETCS)
• image rejection
• output peak power
• quadrature generator
• single-quadrature mixer

In this paper, a RF front-end of the 5.8 GHz integrated CMOS dedicated short range communication (DSRC) transceiver for the Korea/Japan electronic toll collection system is presented. The receiver uses low-IF conversion architecture for high sensitivity and low-power consumption while the transmitter uses direct up-conversion architecture for its simple structure and reliability. To solve image problem in the low-IF receiver, 10 MHz IF and 40 MHz IF are chosen for Korean and Japanese DSRC standards, respectively, since they make no image signals exist in image band. A single-quadrature mixer with the proposed transconductor-type quadrature generator in RF signal path is also adopted which has accurate quadrature characteristic in 5.8 GHz frequency.
When the RF front-end of the integrated 5.8 GHz DSRC transceiver is implemented using 0.13 mu m CMOS technology, the receiver achieves the overall noise figure of less than 5 dB with image rejection ratio of more than 30 dB, and the transmitter carries an output peak power of 10 dBm with the adjacent channel power ratio of -43 dBc. The RF front-end of the 5.8 GHz DSRC transceiver dissipates 45 mA with 1.2 V supply voltage and 142 mA with 1.2/3.3 V dual supply voltage during RX- and TX-modes, respectively.

• 出版日期2010-11