A voltage-controlled oscillator with an ultra-low supply voltage and its application to a fractional-N phase-locked loop

作者：Zhao Bo; Mao Xiaojian; Yang Huazhong^*; Wang Hui

来源：International Journal of Electronics, 2009, 96(9-10): 1011-1022.

DOI：10.1080/00207210902944764

• phase-locked loop (PLL)
• frequency synthesiser
• voltage-controlled oscillator (VCO)
• prescaler
• phase noise

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma-delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 mu m CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is -116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma-delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43-1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is -110 dBc/Hz@1.0 MHz.

• 出版日期2009-10
• 单位清华大学