A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100x for Storage Class Memory Applications

作者：Khwa Win San^*; Chang Meng Fan; Wu Jau Yi; Lee Ming Hsiu; Su Tzu Hsiang; Yang Keng Hao; Chen Tien Fu; Wang Tien Yen; Li Hsiang Pang; Brightsky Matthew; Kim Sangbum; Lung Hsiang Lan; Lam Chung

来源：IEEE Journal of Solid-State Circuits, 2017, 52(1): 218-228.

DOI：10.1109/JSSC.2016.2597822

• MLC
• multilevel cell
• PCM
• PCRAM
• resistance drift
• write driver

For multilevel cell (MLC) phase change memory (PCM), resistance drift ( R-drift) phenomenon causes cell resistance to increase with time, even at room temperature. As a result, the fixed-threshold-retention (FTR) raw-bit-error-rate (RBER) surpasses practical ECC correction ability within hours after being programmed. This study proposes a resistance drift compensation (RDC) scheme to mitigate R-drift issue. The proposed RDC scheme realizes PCM drift compensation and features RDC pulse to suppress ECC decoding failure. The proposed approach was validated using a 90-nm 128M cells PCM chip and an FPGA-based memory controller verification system. The MLC PCM FTR RBER has been suppressed by over 100x, thereby bringing it within ECC capability. The effectiveness of the RDC scheme was verified up to 106 cycles.

• 出版日期2017-1
• 单位清华大学; IBM