摘要

Steady increase of functionality and concurrent reduction of the package size are one of the key driving forces in electronics production. In this paper we will present solutions developed at the institute for the automated assembly of highly miniaturized flip-chips with pitches down to 100 mu m. In particular the present and future influences of miniaturization on the main process steps wafer bumping, component placement, reflow soldering and inspection are examined as well as the influences on complementary materials used. Results regarding the achievable yield after assembly and the reliability of the structures will be presented in addition to an analysis of the failure mechanisms.

  • 出版日期2010