摘要

The design of a frequency divider (FD) employing 3D helical inductors fabricated in the 0.18-mu m IP6M CMOS technology is reported. The LC resonators consist of two 3D helical inductors and varactors. The aim of using 3D inductor is to reduce chip size, the inductance of inductor is designed to be 2 nH, and the size of the inductor is 155 x 155 mu m(2). The divide-by-2 LC-tank injection locked FD is performed by adding an injection nMOS between the differential outputs of the divider with the structure of cross-coupled n-core VCO that contains a tapped LC resonator. The measurement results show that at the supply voltage of l V, the divider free-running frequency is tunable from 2.496 to 2.04 GHz, and at the incident power of 0 dBm the locking range is about 1.31 GHz (30%), from the incident frequency 3.84-5.12 GHz. The core power consumption is 2.59 mW. The die area is 0.664 x 0.737 mm(2).

  • 出版日期2007-6