A 360 fJ/conversion-step, 14-bit, 100 MS/s, digitally background calibrated pipelined ADC in 130-nm CMOS

作者：Larsson A^*; Silva Martinez J; Soenen E G

来源：Analog Integrated Circuits and Signal Processing, 2014, 81(1): 153-164.

DOI：10.1007/s10470-014-0376-z

• Background calibration
• Capacitor mismatch and gain calibration
• Digital ADC calibration
• Pipelined analog-to-digital converter

This paper describes a 14-bit digitally background calibrated pipeline analog-to-digital converter (ADC) implemented in a mainstream 130-nm CMOS technology. The proposed calibration technique linearizes the digital output to correct for errors resulting from capacitor mismatch, finite amplifier gain, voltage reference errors and differential offsets. The software-based calibration technique requires quite modest digital resources and its estimated dynamic power is under 1 % of the ADC power consumption. After calibration, the 14-bit ADC achieves a measured peak Signal-to-Noise-plus-Distortion-Ratio of 71.1 dB at 100 MS/s sampling rate. The worst-case integral nonlinearity is improved from 32.9 down to 4 Least-Significant-Bits after calibration. The chip occupies an active area of 1.25 mm 2 and the core ADC (S/H+ analog+digital power) consumes 105 mW. The Figure-of-Merit is 360 fJ per conversion-step.

• 出版日期2014-10