LOW CLOCK-SWING TSPC FLIP-FLOPS FOR LOW-POWER APPLICATIONS

作者：Hu Yingbo^*; Zhou Runde

来源：Journal of Circuits, Systems, and Computers, 2009, 18(1): 121-131.

DOI：10.1142/s0218126609004971

• Flip-flops
• low clock-swing
• low power
• TSPC

In this paper, two types of Low Clock-Swing True Single Phase Clock (TSPC) Flip-Flops suitable for low-power applications are proposed. One is Low Clock-Swing Edge-Triggered TSPC Flip-Flop (LCSETTFF), constructed with a negative TSPC split out latch and a positive TSPC split out latch. The other is Low Clock-Swing Pulse-Triggered TSPC Flip-Flop (LCSPTTFF), developed in several styles. A double-edge triggered pulse generator is also developed for LCSPTTFF. With low threshold voltage clock transistors adopted, great power efficiency can be obtained in the clock network. Both types of Flip-Flops have advantages of simple structure, low power and much lower clock network power dissipation. All proposed circuits are simulated in HSPICE with 0.18 mu m CMOS technology. Simulation results show that the power of LCSETTFF can be reduced by 42%, while the power dissipation, Power-Delay Product (PDP) and Area-Power-Delay Product (APDP) of LCSPTTFF can be reduced by 45-60%, 11-27% and 58-65%, respectively. In addition, the power consumptions of clock network of LCSPTTFF and LCSETTFF are estimated to be reduced by 78% and 56%, respectively, compared with conventional Flip-Flops.

• 出版日期2009-2
• 单位清华大学